1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a redundancy circuit for use with the semiconductor memory device.
2. Discussion of the Related Art
Improving the yield of a semiconductor memory device is typically an important matter that should be considered when manufacturing the semiconductor memory device. Generally, if a semiconductor memory device has one or a few defective memory cells, it cannot be shipped as a product for use in the marketplace. In some fields, however, such as those that utilize an automated response function, devices manufactured for use therein, such as a dynamic random access memory (DRAM), a static random access memory (SRAM) and an electrically erasable and programmable read only memory (EEPROM) that have defective memory cells, may still be used in the marketplace.
The probability that a defective memory cell will be generated when a high density semiconductor memory device is manufactured is greater than that of when a low density semiconductor memory device is manufactured. This typically occurs, as the higher density semiconductor memory device is affected by difficulties such as debris, during the manufacturing process. Because the semiconductor memory device is affected by debris, the yield is lowered further. Therefore, various attempts have been made to increase the yield of a high density semiconductor memory device.
To obtain a high yield semiconductor memory device, defective memory cells that may be generated when manufacturing the semiconductor memory device should be suppressed. However, current efforts employed to suppress the generation of defective memory cells have certain limitations. Accordingly, additional techniques for improving the yield have been suggested. One such technique is to save the defective areas or cells that are generated during the manufacturing process of a semiconductor memory device by modifying the construction of the semiconductor memory device.
A redundancy technique is typically used to save the defective areas or cells generated during the manufacture of a semiconductor memory device. According to the redundancy technique, a memory device, for use therein, includes a main memory cell array for storing binary data and redundant (or spare) memory cell arrays organized in rows and columns. If a few or thousands of defective memory cells are found during a test procedure performed on the main memory cell, the defective memory cells are replaced with redundant memory cells, and the semiconductor memory device is regarded as non-defective. If the number of the defective memory cells exceeds the number of the allocated redundant memory cells, the semiconductor memory device is generally discarded because it cannot be repaired.
Usually, the redundant memory cell array that is used to substitute for defective memory cells that exist on rows of the main memory cell array is called a row redundancy array. The redundant memory cell array that is used to substitute for defective memory cells that exist on columns of the main memory cell array is called a column redundancy array. In order to substitute the redundant memory cells for the defective memory cells, a circuit for storing repair addresses and a circuit for determining whether an address inputted from the outside is identical to the repair addresses are required. These circuits are typically called redundancy circuits. A row redundancy circuit decodes an arbitrary row address, and replaces a defective row area with a corresponding row area of the redundant memory cell array when the decoded row address is identical to any one of the repair addresses. Similar to the row redundancy circuit described above, a column redundancy circuit compares the column address with the stored repair addresses, and replaces defective column areas of the main memory cell array with a corresponding column area of the redundant memory cell array.
In typical redundancy techniques, the circuits for storing repair addresses should have non-volatile memory characteristics. These redundancy techniques include a technique for using a fuse circuit (known as a “program circuit” because fuses are selectively blown out to program (store) repair addresses therein) having a plurality of fuses made of metal, polysilicon, etc. for storing repair row addresses, and a technique for using a nonvolatile memory such as a PROM, EPROM, EEPROM, etc. as a circuit for storing repair row addresses. Of the two techniques, the technique for using the fuse circuit as the circuit for storing repair row addresses has been widely used.
FIG. 1 is a block diagram of a conventional redundancy structure 100. Referring to FIG. 1, when an external address is inputted to a semiconductor memory device embodying, for example, the convention redundancy structure 100, the external address is decoded by a pre-decoder 110 and inputted to a main decoder 120 and a redundancy circuit 130. The external address decoded by the redundancy circuit 130 is then checked. If the external address is identical to a stored repair address, a disable signal is sent to the main decoder 120 and a redundancy enable signal is generated to select a redundant memory cell array 150 instead of a normal memory cell array 140.
FIG. 2 illustrates a conventional redundancy circuit 200. Referring to FIG. 2, the conventional redundancy circuit 200 includes a master fuse circuit M10, address fuse boxes AF1, AF2, and AF3, and an AND gate AND1. The address fuse box AF1 receives eight signals 1–8 obtained by pre-decoding a 3-bit external address DRA2–DRA4 and stores a repair address by blowing out a fuse. The address fuse box AF2 receives four signals 9–12 obtained by pre-decoding a 2-bit external address DRA5–DRA6 and stores a repair address by blowing out a fuse. The address fuse box AF3 receives four signals 13–16 obtained by pre-decoding a 2-bit external address DRA7–DRA8 and stores a repair address by blowing out a fuse. The AND gate AND1 receives outputs of the address fuse boxes AF1–AF3, and outputs a redundancy enable signal RED.
The address fuse boxes AF1–AF3 include a plurality of transistors and fuses F1–F16. Each of the transistors receives an output of the master fuse circuit M10 at a gate thereof. The fuses F1–F16 are each connected to one of the plurality of transistors.
The master fuse circuit M10 determines whether the redundancy circuit 200 is to be used and if the redundancy circuit 200 is used, it determines whether the repair address stored in the fuse boxes AF1–AF3 is identical to the inputted address. If the stored repair address is identical to the inputted address, a redundant memory cell of the redundant memory cell array 150 is accessed.
In the conventional redundancy circuit 200, when an n-bit address is used, 2n fuses are required to store information on the repair address. This is so because an address is stored by connecting the fuses to the 2n signals, which are obtained by decoding an n-bit address, when storing a repair address in an address fuse box.
Thus, as described above, the number of the fuses required for the conventional redundancy circuit 200 dramatically increases as the number of the address bits increases resulting in the reduction of fuse pitch as the number of fuses in fuse boxes having the same size increases.
FIG. 3 illustrates a fuse pitch and the size of a spot for melting a fuse. Referring to FIG. 3, when the number of the fuses in the same area increases and the fuse pitch is reduced, the size of the spot used by repair equipment for melting a fuse should also be reduced. However, efforts to reduce the size of the spot used by the repair equipment have certain limitations. Accordingly, a fuse box structure where spots are focused in two lines is employed to increase the number of fuses without reducing the fuse pitch.
FIG. 4 illustrates structures of a first type fuse box, in which spots are focused in a line, and a second type fuse box, in which spots are focused in two lines. As shown in FIG. 4, the fist type fuse box structure allows more fuses to be formed in the same area without reducing the fuse pitch in comparison with the second type fuse box structure. The second type fuse box structure requires a long fuse resulting in an increased size of the semiconductor memory device.
When the fuses are cut, all the fuses of the first type fuse box are cut only by moving a cutting machine once, for example, in a forward direction, but all the fuses of the second type fuse box can be cut by moving a cutting machine twice, for example, in the forward direction and a rearward direction as shown in FIG. 4. Thus, both fuse box structures take a long time to cut and repair.